The present invention relates to a probe arrangement which is effective for performing a burn-in screening applied to a plurality of semiconductor devices of a wafer condition at a time. The burn-in screening is performed to enhance the reliability of semiconductor devices.
Conventionally, to enhance the reliability of semiconductor devices, the screening of semiconductor devices is performed in the following manner. Each semiconductor device is subjected to a rated or a slightly excessive voltage supplied from an electric power source. The burn-in screening takes several hours. During the burn-in screening, a pseudo signal resembling to an actual operation signal is applied to each signal input electrode, while the semiconductor device is continuously exposed to a high-temperature environment of approximately 125xc2x0 C.
According to a conventional burn-in screening method, a plurality of semiconductor devices are assembled as a package and are subjected at a time to the burn-in screening.
On the other hand, a new burn-in screening method has been recently proposed. The new burn-in screening method is characterized in that the burn-in screening is applied to wafer-state semiconductor devices, such as bare chips and CSP (chip size package).
To realize the packaged burn-in screening applied to wafer-state semiconductor chips, bonding pads are used. The bonding pads serve as lead electrodes for a plurality of semiconductor chips manufactured at a time on a semiconductor wafer. A signal line is connected to the bonding pad. A signal is thus applied to the bonding pad via the signal line. Usually, the number of semiconductor chips formed together on a wafer surface is in a range from 200 to 1,000. Each semiconductor chip is provided with 20 to 40 bonding pads each being an electrode of 100 xcexcm or a comparable micro size. Thus, the total number of signal lines connected to a single wafer raises up to a higher level of 4,000 to 40,000. Thus, accurate connection of such numerous signal lines to corresponding bonding pads is a key to succeed in the packaged burn-in screening. Regarding a technique relating to a packaged or batch contact of numerous signal lines to a semiconductor wafer, a TPS probe is disclosed in the scientific magazine xe2x80x9cNIKKEI MICRO DEVICExe2x80x9d, 1997, July, from page 126.
FIG. 7 shows a conventional TPS probe card 120 which includes a platelike wiring substrate 71, together with a ceramic ring 72, a PCR (i.e., pressure-sensitive conductive rubber) 73, and a bump-formed membrane 74 provided on an upper surface of wiring substrate 71. The wiring substrate 71 is made of a glass or a comparable material having a thermal expansion coefficient similar to that of a semiconductor wafer. The wiring substrate 71 has a surface brought into contact with the PCR 73. A signal, transmitted from the PCR 73 to the surface of wiring substrate 71, is output to the outside via a wiring arranged on this surface of wiring substrate 71. The PCR 73 is soft and thus has a function of absorbing the altitudinal dispersion of the bonding pads of a semiconductor chip and the bumps of TPS probe card 120. Thus, PCR 73 ensures the transmission of signal from the bumps.
An outer diameter of ceramic ring 72 is smaller than the radial (or longitudinal) size of wiring substrate 71. PCR 73 is located beneath the bump-formed membrane 74 and is positioned within an inner rim of ceramic ring 72. A periphery of bump-formed membrane 74 is tightly held by the ceramic ring 72. The bump-formed membrane 74 includes numerous bumps (104 shown in FIG. 10A) formed on a membrane. Each bump provides electric connection to a corresponding bonding pad of a semiconductor wafer. PCR 73 is placed on an upper surface of wiring substrate 71 and is sandwiched from above by the bump-formed membrane 74.
Published Japanese patent No. 2922486 discloses a practical structure for a TPS probe card consisting of the bump-formed membrane, PCR, and the wiring substrate.
More specifically, as shown in FIGS. 10A and 10B, a circular groove 107 is formed on the wiring substrate 71. The ceramic ring 72 has a circular protrusion 108 formed on the lower surface thereof. The ring groove 107 engages or mates with the circular protrusion 108 when the ceramic ring 72 is assembled on the wiring substrate 71. Thus, the circular groove 107 and the circular protrusion 108 cooperatively fix the position of ceramic ring 72 with respect to the wiring substrate 71.
The wiring substrate 71 has external electrodes 109 formed along an end side thereof. An electric lead extends in the body of wiring substrate 71 to provide electric connection between each external electrode 109 and a corresponding inner electrode.
Numerous bumps 104 are formed on the surface of bump-formed membrane 74. The bumps 104 are located inside the inner rim of ceramic ring 72.
The wiring substrate 71 has screw holes 71a. The bump-formed membrane 74 has screw holes 74a. The ceramic ring 72 has screw holes 72a. The screw holes 71a, 74a, and 72a coincide with each other. The screw holes 71a, 74a, and 72a are the same number and have the same positional relationship.
The PCR 73 and the bump-formed membrane 74 are successively mounted on the upper surface of the wiring substrate 71 in such a manner an electrical path is formed from the bump 104 to the external electrode 109 via the PCR 73.
The ceramic ring 72 is placed on the bump-formed membrane 74 and tightly holds or fixes the periphery of bump-formed membrane 74.
Screws 106 are inserted into the screw holes 72a, 74a, and 71a across the stacked layers of ceramic ring 72, bump-formed membrane 74, and wiring substrate 71. The distal end of each screw 106 is engaged in a hole 71a formed on the wiring substrate 71, thereby firmly fixing the stacked layers of ceramic ring 72, bump-formed membrane 74, and wiring substrate 71 as TPC probe card 120.
FIG. 8 shows the arrangement of a conventional wafer tray unit (i.e., vacuum chuck) 121 combinable with the TPS probe card 120 shown in FIG. 7.
The wafer tray unit 121 shown in FIG. 8 includes a wafer tray 81, a wafer mounting base 82, a seal ring 83, and a vacuum valve 84. The wafer tray 81 is a platelike member. The wafer mounting base 82 is placed on an upper surface of wafer tray 81. The wafer mounting base 82 brings an effect of substantially raising the central portion of wafer tray 81 by an amount equal to the height of wafer mounting base 82. A semiconductor wafer to be inspected is placed on an upper surface of wafer mounting base 82. The seal ring 83 is made of a rubber material. The wafer tray 81 has a groove formed in an outer peripheral region thereof. The seal ring 83 is fitted into and firmly held in this groove of wafer tray 81. When the wafer tray unit 121 is assembled with the TPS probe card 120, the seal ring 83 provides an airtight sealing between them so as to define a vacuum chamber. The seal ring 83 holds a vacuum formed in the vacuum chamber. The vacuum valve 84 is attached to a side surface of wafer tray 81, and is connected to a vacuum pump (not shown).
The wafer tray unit 121 shown in FIG. 8 is assembled with the TPS probe card 120 shown in FIG. 7 in the following manner.
FIGS. 11A and 11B show a conventional alignment apparatus for aligning a semiconductor wafer 91 with respect to the probe card 120. FIG. 11A is a plan view of the alignment apparatus, and FIG. 11B is a side view of the alignment apparatus.
In FIG. 11A, the semiconductor wafer 91 is placed on the wafer tray unit 121. The wafer tray unit 121 has a plurality of holes opened on an upper surface thereof. The semiconductor wafer 91 is fixed on the wafer tray unit 121 by drawing a vacuum through the holes opened on the upper surface of wafer tray unit 121. A heater 121a is provided in the wafer tray unit 121 together with a temperature sensing device (not shown). The heater 121a generates heat and increases the temperature of semiconductor wafer 91. The temperature sensing device detects the temperature of semiconductor wafer 91. A heater control unit (not shown) actuates the heater 121a based on a sensing signal of the temperature sensing device to adjust the temperature of the semiconductor wafer 91 to a desired value.
A probe card alignment camera 122 is fixed to a wafer stage 123 together with the wafer tray unit 121. The probe card alignment camera 122 is directed upward for aligning the probe card 120 positioned above this camera 122. The probe card 120 is held facedown. Thus, the probe card alignment camera 122 picks up an image of bumped surface 125 of probe card 120.
A wafer alignment camera 126 is fixed to a probe card stage 127 together with the probe card 120. The wafer alignment camera 126 is directed downward for aligning the semiconductor wafer 91 and for detecting the position of bonding pads.
An image recognition apparatus (not shown) is associated with the probe card alignment camera 122. The image recognition apparatus detects the position and the height of bumped surface 125 of probe card 120 based on an image of probe card 120 picked up by the probe card alignment camera 122. When the position of probe card 120 is not parallel to the upper surface of wafer tray unit 121, an automatic adjustment is performed first of all to bring the probe card 120 and the upper surface of wafer tray unit 121 into a parallelized condition.
The semiconductor wafer 91 is carried onto the wafer tray unit 121. The alignment apparatus shown in FIGS. 11A and 11B is equipped with an X-axis control motor 129, a Y-axis control motor 128, and a xcex8 control motor 130. The X-axis control motor 129 controls an X-axis position of the semiconductor wafer 91. The Y-axis control motor 128 controls a Y-axis position of the semiconductor wafer 91. The xcex8 control motor 130 controls an angle xcex8 of the semiconductor wafer 91. In other words, the X-axis control motor 129, the Y-axis control motor 128, and the xcex8 control motor 130 cooperate as alignment means for controlling the position/direction (i.e., X, Y and xcex8) of semiconductor wafer 91 in a horizontal plane. Under the control of these motors 128, 129 and 130, the semiconductor wafer 91 shifts on an X-Y plane and stops at a predetermined position just below the probe card 120.
The alignment apparatus is further equipped with a Z-axis control mechanism 131. The Z-axis control mechanism 131 raises the wafer tray unit 121 in the up-and-down direction. The semiconductor wafer 91 mounted on the wafer tray unit 121 is thus raised in the up-and-down direction (i.e., in the Z-axis direction). The semiconductor wafer 91 contacts the probe card 120, while the probe card 120 is supported facedown by the probe card stage 127.
FIG. 9 shows an assembled condition of the TPS probe card 120 and the wafer tray unit 121, with the semiconductor wafer 91 interposed or sandwiched between the TPS probe card 120 and the wafer tray unit 121.
In FIG. 9, the semiconductor wafer 91 is an object to be subjected to a burn-in inspection. The semiconductor wafer 91 is placed on the wafer mounting base 82. The bump-formed membrane 74 is positioned on the semiconductor wafer 91 placed on the wafer mounting base 82. The lower surface, i.e., bumped surface 125, of bump-formed membrane 74 is brought into contact with an upper surface of semiconductor wafer 91 placed on the wafer mounting base 82.
In this assembled condition, the vacuum pump is activated to reduce the inside pressure of the vacuum chamber.
Published Japanese patent No. 2925964 discloses a practical method for vacuumizing the chamber defined by the wafer tray unit and the TPS probe card assembled togther via the seal ring.
The semiconductor wafer 91 is subjected to a measurement for checking electric characteristics under a high-temperature environment. Electric power is supplied to the heater 121a. The wafer tray unit 121 and the semiconductor wafer 91 mounted thereon are heated togther by the heater 121a. Heat of heater 121a is transmitted to the probe card 120 via the semiconductor wafer 91. Thus, the probe card 120 is also heated.
According to the above-described conventional probe apparatus, the wafer tray unit 121 has the seal ring 83 located adjacent to the periphery of semiconductor wafer 91. If the clearance between the seal ring 83 and the semiconductor wafer 91 is large, an atmospheric pressure will act on the wiring substrate 71 and the wafer tray 81 from outside because there is no intervening member supporting the wiring substrate 71 and the wafer tray 81 from inside. The wiring substrate 71 will warpage at its peripheral region. As a result, an excessive pressure is applied onto the bumps of the probe card 120 connected to the peripheral region of the semiconductor wafer 91. On the contrary, a reduced or relatively small pressure is applied onto the bumps of the probe card 120 connected to the central region of the semiconductor wafer 91. Due to insufficiency of the applied pressure, no electric connection will be provided between the central region of the semiconductor wafer 91 and the bumps of the probe card 120. As a result, the electric connection between the semiconductor wafer 91 and the probe card 120 becomes unstable.
The above-described conventional probe apparatus employs a structure for utilizing the atmospheric pressure to apply a necessary pressure to the bumps of the probe card 120 connected to the semiconductor wafer 91. To this end, the pressure of the chamber defined by the wafer tray unit 121 and the probe card 120 with the seal ring 83 is reduced by the vacuum pump. Accordingly, the available maximum pressure per unit area of the semiconductor wafer 91 is limited to 1 kgf equivalent to the atmospheric pressure.
Considering the above-described unstable factor with respect to the connection between semiconductor wafer 91 and the probe card 120 as well as the available maximum pressure, the pin number (i.e., the number of bonding pads or bumps) per unit area is limited to a predetermined level. Usually, the required load per pin is 13 gf. This means that the pin number for a 8-inch wafer having an area of 314 cm2 (diameter=200 mm) is limited to 20,265 pins. In other words, an average pin number is limited to approximately 64 pins/cm2.
In view of the foregoing problems, the present invention has an object to provide a probe card capable of applying a uniform pressure to a wafer surface and assuring a stable electric connection between the probe card and a semiconductor wafer.
Furthermore, the present invention has an object to provide a probe card enabling a wafer level burn-in screening applied to a semiconductor wafer having 20,000 pins (in this case, bonding pads) or more.
Furthermore, the present invention has an object to provide a related wafer tray unit assembled with the probe card of the present invention.
Moreover, the present invention has an object to provide a probe apparatus comprising the probe card and the related wafer tray unit of the present invention.
To accomplish the above and other related objects, the present invention provides a probe card used for a burn-in screening or inspection applied to a semiconductor wafer. The probe card of the present invention comprises a main body substrate, an elastic member disposed on the main body substrate, a wiring substrate disposed on the elastic member, a spacer disposed on the main body substrate and spaced radially outward from a periphery of the wiring substrate, a plurality of bumps formed on a membrane disposed on the wiring substrate with electric connection between the bumps and a wiring of the wiring substrate, and a holding ring disposed on the spacer for tightly holding a periphery of the membrane.
According to an embodiment of the present invention, it is preferable that the elastic member has higher elasticity at an outer peripheral region thereof compared with elasticity at a central region thereof. The elastic member consists of a plurality of rubber members which are coaxial with each other and are arranged successively in a radial direction. A radially outermost rubber member has highest elasticity. The plurality of rubber members have successively increasing elasticities in such a manner that a radially outermost rubber member has highest elasticity and a radially innermost rubber member has lowest elasticity. The main body substrate is made of a glass or a comparable material. The main body substrate has a radial size larger than that of the wiring substrate. The holding ring has a radial size substantially identical to or slightly smaller than that of the main body substrate. The wiring substrate is entirely involved within an area defined by an inner rim of the holding ring. A radial gap between the holding ring and the wiring substrate is in a range from {fraction (1/20)} to ⅕ of a diameter of the semiconductor wafer. The spacer has a radial size substantially identical to or slightly smaller than that of the main body substrate and is larger than that of the wiring substrate.
Furthermore, according to an embodiment of the present invention, it is preferable that the elastic member is a single rubber member. The single rubber member has a radial size substantially identical with that of the wiring substrate. The single rubber member has uniform elasticity. The single rubber member has a sufficient thickness for absorbing warpage of the main body substrate. A predetermined amount of warpage is given to the main body substrate beforehand to cancel a bending of the main body substrate when subjected to an external force. A polyimide film is coated on a reverse surface of the main body substrate so as to counteract the bending of the main body substrate.
The present invention provides a wafer tray unit used for a burn-in screening or inspection applied to a semiconductor wafer. The wafer tray unit of the present invention comprises a wafer tray, a wafer mounting base provided on the wafer tray for mounting a semiconductor wafer, a seal ring disposed on the wafer tray and spaced radially outward from a periphery of the wafer mounting base, and a passage formed in the wafer tray with one end of the passage connected to a vacuum valve and the other end of the passage opened into a gap between the seal ring and the wafer mounting base. A radial gap between the seal ring and the wafer mounting base is in a range from {fraction (1/20)} to ⅕ of a diameter of the semiconductor wafer.
The present invention provides a first probe apparatus used for a burn-in screening or inspection applied to a semiconductor wafer. The first probe apparatus comprises a probe card and a wafer tray unit. The probe card comprises a main body substrate, an elastic member disposed on the main body substrate, a wiring substrate disposed on the elastic member, a spacer disposed on the main body substrate and spaced radially outward from a periphery of the wiring substrate, a plurality of bumps formed on a membrane disposed on the wiring substrate with electric connection between the bumps and a wiring of the wiring substrate, and a holding ring disposed on the spacer for tightly holding a periphery of the membrane. The wafer tray unit comprises a wafer tray, a wafer mounting base provided on the wafer tray for mounting a semiconductor wafer, a seal ring disposed on the wafer tray and spaced radially outward from a periphery of the wafer mounting base, and a passage formed in the wafer tray with one end of the passage connected to a vacuum valve and the other end of the passage opened into a gap between the seal ring and the wafer mounting base.
According to the first probe apparatus, the semiconductor wafer is placed on the wafer mounting base of the wafer tray unit and is sandwiched from behind side by the probe card so as to provide electric connection between the bumps of the probe card and bonding pads of the semiconductor wafer. And, the seal ring of the wafer tray unit is brought into contact with the probe card at a portion corresponding to the spacer so as to provide an airtightly closed space between the probe card and the wafer tray unit, the airtightly closed space serving as a vacuum chamber accommodating the semiconductor wafer and communicating with the vacuum valve via the passage formed in the wafer tray.
The present invention provides a second probe apparatus used for a burn-in screening or inspection applied to a semiconductor wafer. The second probe apparatus comprises a probe card, a wafer tray unit, and a reversed tray unit. The probe card comprises a wiring substrate having at least one through hole, a plurality of bumps formed on a membrane disposed on the wiring substrate with electric connection between the bumps and a wiring of the wiring substrate, and a holding ring disposed on the wiring substrate for tightly holding a periphery of the membrane. The wafer tray unit comprises a wafer tray, a wafer mounting base provided on the wafer tray for mounting a semiconductor wafer, a seal ring disposed on the wafer tray and spaced radially outward from a periphery of the wafer mounting base, and a passage formed in the wafer tray with one end of the passage connected to a vacuum valve and the other end of the passage opened into a gap between the seal ring and the wafer mounting base. The reversed tray unit comprises a reversed tray, a reversed mounting base provided on the reversed tray, and a reversed seal ring disposed on the reverse tray.
According to the second probe apparatus, the semiconductor wafer is placed on the wafer mounting base of the wafer tray unit and is sandwiched from behind side by the probe card so as to provide electric connection between the bumps of the probe card and bonding pads of the semiconductor wafer. The seal ring of the wafer tray unit is brought into contact with the probe card so as to provide an airtightly closed space between the probe card and the wafer tray unit, the airtightly closed space serving as a first vacuum chamber accommodating the semiconductor wafer and communicating with the vacuum valve via the passage formed in the wafer tray. And, the reversed seal ring of the reversed tray unit is brought into contact with a behind side of the probe card to provide an airtightly closed space between the probe card and the reversed tray unit which serves as a second vacuum chamber, the second vacuum chamber communicating with the first vacuum chamber via the through hole of the wiring substrate.
According to an embodiment of the present invention, the reversed tray has a size substantially identical to that of the wafer tray. The reversed seal ring of the reversed tray unit has a size substantially identical to that of the seal ring of the wafer tray unit.